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VCO
with phase integration
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-- VHDL-AMS model VCO
with phase integration
-- Southampton VHDL-AMS
Validation Suite - example 6
-- author: Tom
Kazmierski
-- Department of Electronics
and Computer Science, University of Southampton
-- Highfield, Southampton
SO17 1BJ, United Kingdom
-- Tel. +44 2380 593520
Fax +44 2380 592901
-- e-mail: tjk@ecs.soton.ac.uk
-- Created:
2 June 1997
-- Last revised: 25 Aug 2005 (by
Shaolin Wang)
--
-- Description
-- A differential equation,
in which the varying frequency is the
-- time derivative of
phase, is used to model the basic VCO operation.
-- The phase is modelled
as a free quantity local to the architecture.
--
--------------------------------------------------------------------------------
--1. VHDL-AMS Model
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity VCO is
generic(
fc: real := 1.0E6; -- VCO frequency at Vc
df: real :=
0.5E6; -- [Hz/V], frequency characteristic slope
Vc: voltage
:= 0.0 -- centre frequency input voltage
);
port(quantity Vin: in voltage;
terminal
OutTerminal,ground: electrical);
end entity VCO;
architecture PhaseIntegrator of VCO is
constant TwoPi: real := 6.283118530718;
-- 2pi
-- Phase is a free quantity:
quantity Phase : real;
-- define a branch for the output
voltage source
quantity Vout across Iout through
OutTerminal to ground;
begin
if domain =
quiescent_domain use -- set initial condition
Phase == 0.0;
elsif Phase'above(TwoPi) use
-- Phase <= Phase mod TwoPi
Phase == 0.0;
else
-- phase equation
Phase'dot == TwoPi*realmax(0.5E6,
fc+(Vin-Vc)*df);
end use;
--break statement keeps the phase
within 0.. 2pi
break on Phase'above(TwoPi);
-- output voltage source equation
Vout == 2.5*(1.0+sin(Phase));
end architecture PhaseIntegrator;
--------------------------------------------------------------------------------
2. Testbench
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity test_vco is
end entity test_vco;
architecture test of test_vco is
quantity vin: voltage;
terminal outterminal: electrical;
alias ground is ELECTRICAL_REF;
begin
vin==1.0+1.0*sin(1.0e5*math_2_pi*NOW); --Sinusoid Voltage
Source
vco1: entity vco port map (vin=>vin,outterminal=>outterminal,ground=>ground);
end architecture test;
--------------------------------------------------------------------------------
3. Simulation Results
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