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Sigma-Delta Modulator
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-- VHDL-AMS model of
Sigma-Delta Modulator
-- (c) Southampton University
2005
-- Southampton VHDL-AMS
Validation Suite
-- author:
Xianqiang Ren and
Tom Kazmierski
-- Department of Electronics
and Computer Science, University of Southampton
-- Highfield, Southampton
SO17 1BJ, United Kingdom
-- Tel. +44 2380 593520
Fax +44 2380 592901
-- e-mail: xr03r@ecs.soton.ac.uk, tjk@ecs.soton.ac.uk
-- Created: 4 May 2004
-- Last revised:
15 August 2005 (by Shaolin Wang)
--
--------------------------------------------------------------------------------
-- 1. VHDL-AMS Model
of 3rd Order Sigma-Delta Modulator
library
IEEE;
use IEEE.MATH_REAL.all;
use IEEE.STD_LOGIC_1164.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.ELECTRICAL_SYSTEMS.all;
ENTITY sdm3 IS
GENERIC(
c1_value :
real := 1.000000;
c2_value :
real := 1.000000;
c3_value :
real := 1.000000;
b1_value :
real := 1.000000);
PORT(
TERMINAL vin : ELECTRICAL;
SIGNAL clk : IN
STD_LOGIC;
SIGNAL op : OUT
STD_LOGIC);
END ENTITY sdm3;
ARCHITECTURE bhv OF sdm3 IS
TERMINAL adder1o : ELECTRICAL;
TERMINAL adder2o : ELECTRICAL;
TERMINAL adder3o : ELECTRICAL;
TERMINAL inter1o : ELECTRICAL;
TERMINAL a1o : ELECTRICAL;
TERMINAL c1o : ELECTRICAL;
TERMINAL inter2o : ELECTRICAL;
TERMINAL a2o : ELECTRICAL;
TERMINAL c2o : ELECTRICAL;
TERMINAL inter3o : ELECTRICAL;
TERMINAL a3o : ELECTRICAL;
TERMINAL c3o : ELECTRICAL;
TERMINAL b1o : ELECTRICAL;
SIGNAL Qo : STD_LOGIC;
TERMINAL DACo : ELECTRICAL;
BEGIN
adder_1 : entity adder2 GENERIC MAP(A => 1.0,B
=> -1.0)
PORT MAP(ip1 => c1o,ip2 => a1o,op => adder1o);
adder_2 : entity adder4 GENERIC MAP(A => 1.0,B
=> -1.0,C => -1.0,D => 1.0)
PORT MAP(ip1 => c2o,ip2 => a2o,ip3 => b1o,ip4 => inter1o,op => adder2o);
adder_3 : entity adder3 GENERIC MAP(A => 1.0,B
=> -1.0,C => 1.0)
PORT MAP(ip1 => c3o,ip2 => a3o,ip3 => inter2o,op => adder3o);
inter_1 : entity inter PORT MAP(ip =>
adder1o,op => inter1o);
a1 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => DACo,op => a1o);
c1 : entity coefficient
GENERIC MAP( amplitude => 1.000000)
PORT MAP(ip => vin, op => c1o);
inter_2 : entity inter PORT MAP(ip =>
adder2o,op => inter2o);
a2 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => DACo,op => a2o);
c2 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => vin, op => c2o);
inter_3 : entity inter PORT MAP(ip =>
adder3o,op => inter3o);
a3 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => DACo,op => a3o);
c3 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => vin,op => c3o);
b1 : entity coefficient
GENERIC MAP(amplitude => 1.000000)
PORT MAP(ip => inter3o,op => b1o);
Q : entity
quantizer GENERIC MAP(threshod => 0.0)
PORT MAP(clk => clk,ip => inter3o,op => Qo);
DAC_1 : entity DAC GENERIC MAP(MAX
=> 5.0,MIN => -5.0)
PORT MAP(ip => Qo,op => DACo);
op <= Qo;
END ARCHITECTURE bhv;
--------------------------------------------------------------------------------
--2. Adder2
--Used as a two
inputs adder for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY adder2 IS
GENERIC(
A : REAL :=
1.0;
B : REAL :=
-1.0);
PORT(TERMINAL ip1 : ELECTRICAL;
--original input signal
TERMINAL ip2 :
ELECTRICAL; --feedback input signal
TERMINAL op :
ELECTRICAL); --output signal
END ENTITY adder2;
ARCHITECTURE bhv OF adder2 IS
QUANTITY vip1 ACROSS ip1 TO op;
QUANTITY vip2 ACROSS ip2 TO op;
QUANTITY vop ACROSS iop THROUGH op TO ELECTRICAL_REF;
BEGIN
vop == A*vip1 + B*vip2;
END ARCHITECTURE bhv;
--------------------------------------------------------------------------------
--3. Adder3
--Used as a
three inputs adder for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY adder3 IS
GENERIC(
A : REAL :=
1.0;
B : REAL :=
1.0;
C : REAL :=
-1.0);
PORT(TERMINAL ip1 : ELECTRICAL;
TERMINAL ip2 :
ELECTRICAL;
TERMINAL ip3 :
ELECTRICAL;
TERMINAL op :
ELECTRICAL); --output signal
END ENTITY adder3;
ARCHITECTURE bhv OF adder3 IS
QUANTITY vip1 ACROSS ip1;
QUANTITY vip2 ACROSS ip2;
QUANTITY vip3 ACROSS ip3;
QUANTITY vop ACROSS iop THROUGH op TO ELECTRICAL_REF;
BEGIN
vop == A*vip1 + B*vip2 + C*vip3;
END ARCHITECTURE bhv;
-------------------------------------------------------------------------
--4. Adder4
--Used as a four inputs adder for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY adder4 IS
GENERIC(
A : REAL :=
1.0;
B : REAL :=
1.0;
C : REAL :=
-1.0;
D : REAL :=
-1.0);
PORT(TERMINAL ip1 : ELECTRICAL;
TERMINAL ip2 :
ELECTRICAL;
TERMINAL ip3 :
ELECTRICAL;
TERMINAL ip4 :
ELECTRICAL;
TERMINAL op :
ELECTRICAL); --output signal
END ENTITY adder4;
ARCHITECTURE bhv OF adder4 IS
QUANTITY vip1 ACROSS ip1;
QUANTITY vip2 ACROSS ip2;
QUANTITY vip3 ACROSS ip3;
QUANTITY vip4 ACROSS ip4;
QUANTITY vop ACROSS iop THROUGH op TO
ELECTRICAL_REF;
BEGIN
vop == A*vip1 + B*vip2 + C*vip3 + D*vip4;
END ARCHITECTURE bhv;
------------------------------------------------------------------------------
--5. Coefficient
Amplifier
--Used as an
coefficient amplifiers for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY coefficient IS
GENERIC(amplitude : REAL := 1.0);
PORT( TERMINAL ip : ELECTRICAL;
-- input analog signal
TERMINAL op :
ELECTRICAL); -- output analog signal
END ENTITY coefficient;
ARCHITECTURE bhv OF coefficient IS
QUANTITY vip ACROSS ip;
QUANTITY vop ACROSS iop THROUGH op TO
ELECTRICAL_REF;
BEGIN
vop == amplitude * vip;
END ARCHITECTURE bhv;
---------------------------------------------------------------------------
--6. DAC
--Used as an
1-bit Digital-to-Analog Converter for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY DAC IS
GENERIC(MAX : REAL := 5.0;
MIN : REAL :=
-5.0);
PORT(SIGNAL ip : IN STD_LOGIC;
-- input digital signal
TERMINAL op :
ELECTRICAL); -- output analog signal
END ENTITY DAC;
ARCHITECTURE bhv OF DAC IS
SIGNAL inter : REAL := 0.0;
QUANTITY vop ACROSS iop THROUGH op TO
ELECTRICAL_REF;
BEGIN
inter <= MAX WHEN ip = '1' ELSE MIN;
vop == inter'ramp(1.0e-9);
END ARCHITECTURE bhv;
---------------------------------------------------------------------------
--7. Integrator
--Used as an
integrator for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY inter is
PORT(TERMINAL ip : ELECTRICAL;
--input signal
TERMINAL op : ELECTRICAL);
--output signal
END ENTITY inter;
ARCHITECTURE bhv OF inter IS
QUANTITY vop ACROSS iop THROUGH op TO
ELECTRICAL_REF;
QUANTITY vip ACROSS ip;
BEGIN
vop == vip'integ;
END ARCHITECTURE bhv;
----------------------------------------------------------------------------
--8. Quantizer
--Used as a
Quantizer for Sigma-Delta Converters
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
ENTITY quantizer IS
GENERIC(threshod : REAL := 0.0);
PORT( SIGNAL clk : IN STD_LOGIC;
TERMINAL ip :
ELECTRICAL; --input analog signal
SIGNAL op : OUT
STD_LOGIC); --output digital signal;
END ENTITY quantizer;
ARCHITECTURE bhv OF quantizer IS
QUANTITY vip ACROSS ip;
BEGIN
PROCESS(clk)
BEGIN
IF(rising_edge(clk)) THEN
IF
vip'above(threshod) THEN
op <= '1';
ELSE
op <= '0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE bhv;
----------------------------------------------------------------------------
--9. Testbench
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
entity t_sdm3 is
end entity t_sdm3;
architecture bhv of t_sdm3 is
terminal A : electrical;
quantity xin across iin through A to
electrical_ref;
signal op : std_logic;
signal clk : std_logic;
begin
m_sdm3 : entity sdm3 port map(vin => A,clk =>clk,op
=> op);
xin == 5.0*sin(math_2_pi*1.0e6*NOW);
process
begin
clk <= '1';
wait for 500 ps;
clk <= '0';
wait for 500 ps;
end process;
end architecture bhv;
-------------------------------------------------------------------------------
--10. Simulation
Results
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