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Analogue Schmitt trigger
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-- VHDL-AMS model of
Analogue Schmitt trigger
-- (c) University of
Southampton 1997
-- Southampton VHDL-AMS
Validation Suite - example 5
-- author: Tom
Kazmierski
-- Department of Electronics
and Computer Science, University of Southampton
-- Highfield, Southampton
SO17 1BJ, United Kingdom
-- Tel. +44 2380 593520
Fax +44 2380 592901
-- e-mail: tjk@ecs.soton.ac.uk
-- Created:
2 June 1997
-- Last revised:
20 Aug 2005 (by Shaolin Wang)
--
-- Description
-- This Schmitt trigger
uses a signal to model a simple hysteresis
-- loop. When the input
voltage exceeds the high threshold, the internal
-- state switches to
5 Volts and when the input drops below the low threshold,
-- the state switches
to 0 Volts.
-- The output is an
ideal voltage source which contributes to the output
-- terminal OutTerminal.
--
-- Acknowledgement:
-- This example was
developed with the help of Ernst Christen, Analogy Inc.
--
--------------------------------------------------------------------------------
--
1. VHDL-AMS
Model of
Analogue Schmitt trigger
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity AnalogueSchmitt is
generic( -- low and high threshold:
Vtl: voltage
:= 1.2; -- low voltage threshold
Vth: voltage
:= 2.4 -- high voltage threshold
);
port (quantity Vin: in voltage;
-- input
interface quantity
terminal
OutTerminal,ground: electrical); -- terminal driven by a voltage source
end entity AnalogueSchmitt;
architecture Hysteresis of AnalogueSchmitt is
-- declare a signal to memorise the hysteresis state:
signal State: voltage:=5.0 ; -- initial state is low
-- declare a through branch for the output voltage source
quantity Vout across Iout through
OutTerminal to ground;
begin
process
begin
loop
wait until
Vin'above(Vth); -- trigger event when Vin > Vth
State<=0.0;
wait until
not Vin'above(Vtl);-- trigger event when Vin < Vth
State<=5.0;
end loop;
end process;
-- output voltage source equation:
Vout == State'ramp; -- the use of ramp assures that when a discontinuity
-- in State arises, it is announced to the simulator
end architecture Hysteresis;
--------------------------------------------------------------------------------
-- 2. Testbench
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity test_schmitt
is
end entity test_schmitt;
architecture test of
test_schmitt is
quantity vin: voltage;
terminal outterminal:electrical;
alias ground is ELECTRICAL_REF;
begin
vin ==
1.5+1.5*sin(math_2_pi*NOW); -- Sinusoid Voltage Source
analogueschmitt1 :
entity analogueschmitt
port map(vin=>vin, outterminal=>outterminal,ground=>ground);
end architecture test;
--------------------------------------------------------------------------------
--3.
Simulation Results
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