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Phase-Locked Loop Frequency Multiplier
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-- VHDL-AMS model of
Phase-Locked Loop Frequency Multiplier
-- (c) Southampton University
1997
-- Southampton VHDL-AMS
Validation Suite
-- author: Tom
Kazmierski
-- Department of Electronics
and Computer Science, University of Southampton
-- Highfield, Southampton
SO17 1BJ, United Kingdom
-- Tel. +44 2380 593520
Fax +44 2380 592901
-- e-mail: tjk@ecs.soton.ac.uk
-- Created:
30 May 1997
-- Last revised: 28 Aug 2005
(by Shaolin Wang)
--
-----------------------------------------------------------------------------
--
-- Description:
-- This is a mixed-signal
example in which both behavioural and structural
-- descriptions are
used. The digital phase detector and analogue filter
-- architectures are
structures that use standard library components. The VCO
-- architecture is behavioural
and uses the phase integrator described in the
--
example model of
VCO
-- The divide-by-two
counter architecture is behavioural.
--
-----------------------------------------------------------------------------
--1. -- VHDL-AMS
model of Phase-Locked Loop
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;
--- main entity
entity PLLFrequencyMultiplier is
-- input & output terminals
port(terminal InWaveT,OutWaveT,ground:
electrical);
end entity PLLFrequencyMultiplier;
architecture MixedSignal of PLLFrequencyMultiplier is
-- internal signals
signal Scomparator,Up,Down,Scounter,SVCO : std_logic;
-- internal terminals
terminal FilterT :electrical;
-- internal analog quantities
quantity FilterV across FilterT to
ground; -- filter output voltage
quantity VCOV across OutWaveT to ground;
-- VCO output coltage
begin
-- instantiate components
Comparator_L: entity Comparator
port map (PveT => InWaveT, NveT => ground, Sout => Scomparator);
PhaseDetector_L: entity PhaseDetector
port map (In1 => Scomparator, In2 => Scounter, Up => Up, Down => Down);
Filter_L: entity AnalogFilter
port map (Up => Up, Down => Down, FilterT => FilterT,ground=>ground );
VCO_L: entity VCO
port map ( Vin => FilterV, OutTerminal => OutWaveT, ground=>ground );
-- convert analog VCO output to digital
SVCO <='1' when VCOV'above(2.5)
-- logic threshold 2.5V
else '0' ;
Counter_L: entity Counter
port map ( Input => SVCO, Output => Scounter);
end architecture MixedSignal; --
PLLFrequencyMultiplier
--------------------------------------------------------------------------------
--2. VHDL Model of
Comparator
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
use IEEE.std_logic_1164.all;
-- Behavioral model of the comparator
entity Comparator is
generic( Vthreshold: voltage := 0.0);
-- [V] comparator threshold level
port(terminal PveT,NveT: electrical;
-- analog input pins
signal SOut: out
std_logic -- digital output
);
end entity Comparator ;
architecture Behavior of Comparator is
quantity DeltaV across PveT to NveT;
-- differential input voltage
begin
-- the architecture consists of one
concurrent signal assignment statement
Sout <='1' when DeltaV'above(Vthreshold)
-- trigger event when V+>V- +Vth
else '0' ; -- trigger event when V+<V- -Vth
end architecture Behavior;
--------------------------------------------------------------------------------
--3. VHDL-AMS Model
of RS Flip-Flop
library IEEE;
use IEEE.std_logic_1164.all;
-- digital behavioral model of RS flip-flop
entity RSFF is
generic (DelayQ, DelayQB: TIME := 1 ns);
port ( R,S: in std_logic;
Q,QB: out
std_logic);
end entity RSFF;
architecture Behavior of RSFF is
signal Qin: std_logic:='0';
signal QBin: std_logic:='0';
begin
Qin<= '0' when R='1'and S='1' else
'0' when
R='1'and S='0' else
'1' when
R='0'and S='1' else
not QBin
after 1ns;
QBin<= '0' when R='1' and S='1' else
'1' when
R='1' and S='0' else
'0' when
R='0' and S='1' else
not Qin
after 1ns;
Q<=Qin after 1 ns;
QB<=QBin after 1 ns;
end architecture Behavior; -- RSFF
--------------------------------------------------------------------------------
--4. digital phase detector
library IEEE;
use IEEE.std_logic_1164.all;
-- digital phase detector
entity PhaseDetector is
port( In1,In2 :in std_logic;
-- inputs
Up,Down :out
std_logic -- outputs
);
end entity PhaseDetector;
architecture Structure of PhaseDetector is
-- internal phase detector signals
signal UpB,DownB,Top,TopB,Bottom,BottomB,Reset :
std_logic;
begin
Reset<= UpB nor DownB after 2 ns;
RST: entity RSFF
port
map(R=>UpB, S=>Reset, Q=>Top, QB=>TopB);
RSB: entity RSFF
port
map(R=>Reset, S=>DownB, Q=>Bottom, QB=>BottomB);
RSUp: entity RSFF
port map(R=>In1,
S=>Top, Q=>UpB, QB=>Up);
RSDown: entity RSFF
port map(R=>BottomB,
S=>In2, Q=>Down, QB=>DownB);
end architecture Structure; -- PhaseDetector
--------------------------------------------------------------------------------
--5. analog filter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.electrical_systems.all;
entity AnalogFilter is
generic (InCurrent : current :=
100.0E-6; -- [A] input current
R1: REAL := 100.0E3; -- filter component values
R2: REAL := 10.0E3;
C1: REAL := 100.0E-12;
C2: REAL := 3.3E-9
);
port ( signal Up,Down: in std_logic;
-- input signals to control current sources
terminal
FilterT,ground: electrical -- analog output pin
);
end entity AnalogFilter;
architecture Circuit of AnalogFilter is
terminal Vc1T,Vc2T :electrical;
-- internal filter nodes
quantity Isource through Vc1T to ground;
-- current source
begin
-- simultaneous equation to model the current source
if Up = '1' and Down = '0' use
Isource == -InCurrent;
-- 100mA
elsif Up = '0' and Down = '1' use
Isource == InCurrent;
-- -100ma
else
Isource == 0.0;
-- no current
end use;
-- circuit components (models defined
in analog_components)
Capacitor1: entity capacitor generic map
(C1) port map(Vc1T,ground);
Resistor1: entity resistor generic map (R1)
port map(Vc1T,filterT);
Resistor2: entity resistor generic map (R2)
port map(FilterT,Vc2T);
Capacitor2: entity capacitor generic map (C2)
port map(Vc2T,ground);
end architecture Circuit; -- AnalogFilter
--------------------------------------------------------------------------------
-- 6. VCO model with phase
integration (see the example model of VCO)
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity VCO is
generic(
fc: real :=
1.0E6; -- VCO frequency at Vc
df: real :=
0.5E6; -- [Hz/V], frequency characteristic slope
Vc: voltage
:= 0.0 -- centre frequency input voltage
);
port(quantity Vin: in voltage;
terminal
OutTerminal,ground: electrical);
end entity VCO;
architecture PhaseIntegrator of VCO is
constant TwoPi: real := 6.283118530718; -- 2pi
-- Phase is a free quantity:
quantity Phase : real;
-- define a branch for the output
voltage source
quantity Vout across Iout through
OutTerminal to ground;
begin
if domain = quiescent_domain use
Phase == 0.0;
elsif Phase'above(TwoPi) use
Phase == 0.0;
else
Phase'dot == TwoPi*realmax(0.1E6,
fc+(Vin-Vc)*df);
end use;
break on Phase'above(TwoPi);
-- output voltage source equation
Vout == 2.5*(1.0+sin(Phase));
end architecture PhaseIntegrator;
--------------------------------------------------------------------------------
-- 7. a behavioral model
of the digital counter
library IEEE;
use IEEE.std_logic_1164.all;
-- a behavioral model of the digital counter
entity Counter is
generic (Count: positive := 2; -- divide-by-two by
default
Delay:
TIME := 0 ns -- propagation delay
);
port (Input : in std_logic;
-- input and output
pins
Output : out std_logic);
end entity Counter;
architecture Behavioral of Counter is
begin
-- declare a process with a variable to memorise counter state
process(Input) is -- process is triggered by an input event
variable CurrentCount : natural := 0; -- count memory
begin
if Input='1' then -- a rising edge occured
CurrentCount := (CurrentCount+1) mod Count;
-- flip the output every Count/2 pulses
if CurrentCount < Count / 2
then
Output <= '0' after Delay;
else Output <= '1' after Delay;
end if;
end if;
end process;
end architecture Behavioral; -- Counter
--------------------------------------------------------------------------------
--8. Resistor
library IEEE;
use IEEE.electrical_systems.all;
entity resistor is
generic (res : resistance); --
resistance (no initial value)
port (terminal p1, p2 : electrical);
end entity resistor;
architecture ideal of resistor is
quantity v across i through p1 to
p2;
begin
-- Fundamental equation
v == i*res;
end architecture ideal;
--------------------------------------------------------------------------------
--9. Capacitor
library IEEE;
use IEEE.electrical_systems.all;
entity capacitor is
generic (cap: capacitance); --
Capacitance [F]
port (terminal p1, p2 : electrical);
end entity capacitor;
architecture ideal of capacitor is
quantity v across i through p1 to
p2;
begin
if domain=quiescent_domain use
v== 0.0;
-- initial condition
else
i == cap * v'dot;
-- Fundamental equation
end use;
end architecture ideal;
--------------------------------------------------------------------------------
--10. Testbench
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
entity test_pll is
end entity test_pll;
architecture test of test_pll is
terminal InWaveT,OutWaveT: electrical;
alias ground is ELECTRICAL_REF;
begin
vs: entity vsin generic map
(freq=>1.0e5,amplitude=>5.0) --Sinusoid Voltage Source
port map (pos=>InWaveT,neg=>ground);
pll1: entity pllfrequencymultiplier
port map(InWaveT=>InWaveT,OutWaveT=>OutWaveT,ground=>ground);
end architecture test;
--------------------------------------------------------------------------------
--11. Sinusoid
Voltage Source
library IEEE;
use IEEE.MATH_REAL.all;
use IEEE.ELECTRICAL_SYSTEMS.all;
entity vsin is
generic (
freq : real;
-- frequency [Hertz]
amplitude :
voltage; -- amplitude [Volts]
phase : real
:= 0.0; -- initial phase [Degrees]
offset :
voltage := 0.0); -- DC value [Volts]
port (terminal pos, neg : electrical);
end entity vsin;
architecture ideal of vsin is
-- Declare Branch Quantities
quantity v across i through pos
to neg;
-- Declare Quantity for Phase in
radians (calculated below)
quantity phase_rad : real;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
v == offset + amplitude * sin(phase_rad);
end architecture ideal;
--------------------------------------------------------------------------------
--12. Simulation
Results
--In the beginning
-- Phase Locked
-- control voltage
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